The invention relates to an SD-ADC (sigma delta analog/digital converter).
This application claims the benefit of the Aug. 29, 2001 priority date of German patent application 101 42 191.5, the contents of which are herein incorporated by reference.
U.S. Pat. No. 5,073,777 describes sigma delta analog/digital converters that operate in parallel with one another with independent dither signal generators. The sigma delta analog/digital converter contains at least one integrator and a comparator or quantizer for the analog/digital conversion of an analog input signal. Furthermore, a dither signal generator for generating a digital dither signal is provided.
U.S. Pat. No. 5,010,347 discloses an analog/digital converter with a high signal-to-noise ratio. The analog/digital converter likewise contains an integrator and a comparator for the analog/digital conversion of an analog input signal. Furthermore, a noise generator for generating a digital noise signal is provided.
Young C. A.: xe2x80x9cTHE ADVANTAGES OF STRICTLY DIGITAL DITHERxe2x80x9d in IEE Colloquium on advances analog/digital and digital/analog conversion technique applications, London, UK, 1989, pages 2/1-2/3, describes the use of a digital dither signal in an analog/digital converter, the digital dither signal being added to the digital circuit regions downstream of the analog/digital converter.
SD-ADC generally exhibit limit cycles (periodic audible free oscillation of the ADC with time constant xcfx84t), which are perceptible as interference signal in the area primarily in audio applications. Limit cycles occur principally when a constant signal is present at the input of the SD-ADC, or during a transmission intermission in which no audio signal is transmitted (so-called idle tones).
In order to avoid such limit cycles, at suitable points in time, a random signal (dither signal) is fed into the SD-ADC, which signal brings about a certain variance of the input signal and thus reduces the proportion of the interference frequency in the spectrum of the output signal. To date, the dither signal has usually been fed to the SD-ADC in analog form.
FIG. 1 shows a block diagram of a known SD-ADC with analog dither signal feed-in. The SD-ADC illustrated is a two-stage SD-ADC with a feedback loop 6 (second order single loop SD-ADC), with two integrators 1 (only one of which is shown), at whose input an analog signal is present, and a comparator 2. The SD-ADC furthermore comprises a dither signal generator 4 for generating a digital dither signal that, after D/A conversion by means of a dither DAC 10, is added to the analog output signal of the second integrator 1 (addition node 12). The accumulated analog signal is fed to the comparator 2, whose switching threshold is usually 0V. Finally, the comparator outputs a corresponding digital value at its output.
The digital result is buffer-stored in a buffer 11 that is connected to the inputs of the integrators 1 via the feedback path 6. In addition, the digital result is fed to signal processing connected downstream (not shown).
The SD-ADC illustrated has the disadvantage, in particular, that the addition of an analog dither signal generates additional interference that adversely influences the performance of the SD-ADC. Furthermore, the known SD-ADC requires an additional dither DAC that, in today""s CMOS technologies, requires a relatively large amount of area and power.
Owing to the proximity of the feed-in of the analog dither signal to a highly nonlinear comparator, the feed-in of the dither signal at this location is particularly critical.
Therefore, the object of the present invention is to provide an SD-ADC that requires less area and power for the feed-in and processing of dither signals in today""s CMOS technologies.
The essential concept of the invention consists in carrying out the feed-in of the dither signal in the digital part of the SD-ADC, in feeding only the analog output signal of the integrator to the comparator, and in reinterpreting or changing the digital result output by the comparator in a manner dependent on the level of the dither signal. This means shifting more functionality into the digital region, since modern CMOS processes enable much smaller digital structures than analog structures.
For this purpose, a plurality of comparators with different switching thresholds are provided, which convert the analog signal fed from the integrator into a digital value. Furthermore, a digital logic unit connected to the output of the comparators is provided, to which the digital dither signal is fed and that changes the digital value output by the comparators in a manner dependent on the level of the dither signal.
In this case, the switching thresholds of the comparators preferably correspond to the possible levels of the dither signal.
The SD-ADC is preferably of fully differential construction, the comparators having positive and negative switching thresholds. In this case, the SD-ADC comprises at least three comparators.
In accordance with a preferred embodiment of the invention, the logic unit firstly checks the output of that comparator whose switching threshold corresponds to the negative dither signal level, and then changes, if appropriate, the bits at the outputs of the comparators with a switching threshold that is smaller in magnitude.
The digital result output by the digital logic unit is preferably fed back to the respective inputs of the integrators.
It has been shown that, for the dither signal processing, it is possible to use very simple comparators whose switching threshold is, in particular, significantly less accurate than in the case of comparators of the quantizer of the SD-ADC.